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New AEM Platform Boosts AI and HPC Chip Testing

2026-08-21
Latest company news about New AEM Platform Boosts AI and HPC Chip Testing

As the global AI computing race intensifies, the stability of computing infrastructure has emerged as a decisive factor separating industry leaders from competitors. When an AI processor handles trillions of floating-point operations in data centers, even minor early-stage failures can cripple entire computing clusters, potentially causing catastrophic economic losses and service disruptions. For chip manufacturers, maintaining product reliability under advanced process nodes while controlling expensive testing costs has become a high-stakes balancing act.

AEM, a global leader in semiconductor testing solutions, has unveiled its next-generation Automated Burn-in Platform System (AMPS-BI). Designed specifically for high-performance computing (HPC) and AI processors, this system employs high-parallelism, high-power stress testing to identify latent defects before products leave the factory, establishing a robust reliability foundation for AI-era computing infrastructure.

Addressing the Testing Challenges of Advanced Nodes

As Moore's Law approaches physical limits, AI chips are rapidly migrating to cutting-edge process nodes (3nm, 2nm). While heterogeneous integration and chiplet packaging technologies deliver performance breakthroughs, they simultaneously create testing complexities that traditional methods struggle to address.

Insufficient test coverage, thermal management failures, and prohibitive downtime costs have become major bottlenecks in mass production. The AMPS-BI system tackles these challenges by combining automated efficiency with revolutionary thermal management capabilities, offering semiconductor manufacturers a balanced solution for performance and cost.

Breakthrough Technology: Intelligent Thermal Control Meets Parallel Architecture

The system's patented multi-zone Intelligent Thermal Control (ITC) technology represents a quantum leap in testing precision. During burn-in procedures, high-performance AI chips operating under extreme loads frequently develop localized hot spots that can distort test results or damage expensive samples.

AMPS-BI achieves chip-level thermal stability control, supporting individual device power loads up to 2KW. This ensures accurate temperature regulation regardless of computational complexity, effectively exposing potential defects while eliminating false positives from thermal runaway.

The platform's architectural innovations include:

  • High-parallel automation: Simultaneous testing of hundreds of devices dramatically reduces cycle times and boosts production throughput
  • Application-specific instrumentation: Configurable testing parameters optimized for different use cases and yield requirements
  • Asynchronous control: Independent operation per chip enables real-time mode switching and eliminates idle capacity
  • Advanced packaging compatibility: Supports large-form-factor packages exceeding 100mm x 100mm with versatile socket adaptation
  • Industry 4.0 integration: JEDEC-standard I/O interfaces enable seamless smart factory automation
From Burn-in to System-Level Validation

AMPS-BI's modular design bridges the traditional gap between burn-in and system-level testing (SLT). The platform's future-ready architecture allows effortless upgrades to SLT and three-temperature testing capabilities, providing AI chip designers, foundries, and OSAT providers with long-term investment protection without requiring costly equipment replacement.

Industry Validation: Establishing a New Testing Paradigm

AEM CEO Amy Leong stated: "With over 1,000 deployed burn-in and SLT systems worldwide, AMPS-BI represents more than an upgrade—it's a strategic enabler helping clients accelerate product development and secure competitive advantage in the AI computing market."

The system has already gained market validation, with a leading HPC/AI chip designer recently adopting AEM's solution as its plan-of-record testing platform. As AEM advances its "Test 2.0" framework, AMPS-BI is positioning itself as essential infrastructure for next-generation logic device validation.

In an era of exponential AI computing demand, chip reliability has transcended technical specifications to become a strategic imperative. AEM's AMPS-BI not only delivers cutting-edge testing capabilities but also reinforces the semiconductor supply chain's capacity to meet tomorrow's challenges. As AI adoption accelerates, AEM continues to drive innovation in test technology, powering the global transition toward advanced intelligent computing.

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